LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: NansonHuang at ITRI.ORG.TW<NansonHuang@I...>
    Date: Thu Dec 18 13:43:35 CET 2003
    Subject: [oc] Register Allocation Problems ?
    Top

    hi,

    Now I am thinking a problem. If there are 5 parameters needed assigned to
    the register for example on AMBA-AHB or Wishbone, processor could control
    the module via R/W the 5 parameters. Thus, we need to deal with the
    register alocation to define the register. It comes up with such many ways
    to assign each parameter to a 32-bits wide
    register. If A paramater is 1 bit, B is 2 bits, C is 9 bits, D is 7 bits, E
    is 16 bits,
    should we put as many as bits in one 32-bits register, i.e. to increase the
    register density for less register access ? However, the driver needs to
    pack or unpack the registers to extract/put the information it need. It
    also takes time and slow down the
    response time of the driver. What's the generally way to deal with it ? How
    to balance it ? Should we divided the 32-bits register as 4 or 8 -bits per
    block and just put one parameter to it for easy s/w decode ? For example,

    0000000A000000B0000000C as a 32-bits register where A is 1-bit, B is 2
    bits, C is 9-bits.

    Appreciate for your any comments. Thanks

    Nanson




    Follow upAuthor
    [oc] Register Allocation Problems ?Joachim strombergson

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.