|
Message
From: John Sheahan <jrsheahan@o...>
Date: 29 Nov 2003 10:12:44 +1100
Subject: Re: [oc] verilog or vhdl - Let's finish this discussion ?
Come on Guys
Can't we just agree that both languages get used for
lots of real work and can used to do good things, and move on?
Prove your favorite language is better if you feel the need
Release a design using your preferred language
thats clearly nicer / synthesises faster+smaller /
is more maintainable / testbenches more cleanly /
<fill in the blanks here> .
John
On Fri, 2003-11-28 at 12:18, LuÃs Vitório Cargnini wrote:
<snip>
|
Browse
