|
Message
From: Vic <vikrantps@y...>
Date: Fri, 28 Nov 2003 14:48:22 -0800 (PST)
Subject: Re: [oc] verilog or vhdl - Let's finish this discussion ?
Hi buddy,
Yes what you say is somewhat true. But finally it
depends on what application/project you are working.
In my case I 1st learnt Verilog and found it to be
interesting (for Alterra FPGA). Then for my other
course project I was told 'work using VHDL' (Xilinx
FPGA). Being comfortable with Verilog, I found this
reverse adjustment quite tedious. Guess I am well off
in both languages now. Still I feel Verilog kinda
integrates everything together (other environments or
socket programming). But VHDL is not that advanced and
good for stand-alone designs on FPGAs.
Njoy the weekend.
Vic.
--- Luís_Vitório Cargnini <cargnini@m...>
wrote:
> Vic nad tha other members,
> Excuse me but you are been to enthusiat whne you say
> that VHDL is only
> for geeks and Degree students and researchers.
> I work with both languages Verilog and VHDL. Memory
> is better to be made
> using Verilog, because synthesizers like Leonardo
> Spectrum see that the
> code defined is a memory and use the bit rams of a
> device if available,
> in VHSDl not ever this happens but in VHDL you could
> create more complex
> Structures like matrix of 12x12 (example only)
> std_logc_vectors(32 dowto
> 0) so 12x12x32 and its a two dimensional matrrix now
> try to do this on
> Verilog is almost impossible. Verilog have only 17
> nos synthesizable
> reserved words like fork and join ( i don't readed
> tha Verilog 2001
> specification yet, only in Quartus II ver 3.0 for
> example was added this
> kind of support), but VHDL has a bigger list of non
> synthesizable
> reserved words.
> YES Verilog it's simple very simple, YES VHDL is
> more complex but not
> much more than Verilog, you only need to choose the
> best option for your
> project, entirely or some components of your
> projects. Finally the best
> langauage is that work, if Java did the work good
> (this was a little
> joke), try to get the best approach combinig the
> advance of two
> languages is the better so if Verilog is better to
> define memories, use
> Verilog for this, i fVHDL is better to define more
> complex strtuctures
> so use, don't close your horizons for only one
> language try use teh
> necessary tools to make your project in a adequate
> time, with adequate
> pricing.
>
>
> On Thu, 20 Nov 2003 09:01:19 -0800 (PST)
> Vic <vikrantps@y...> wrote:
>
> > HaHa, I agree with Paul to some extent...even I
> worked
> > on a 'medium' sized graduate project on VHDL in
> the
> > last 3 months. To be frank VHDL sucks!
>
> --
> Thanks && Regards
> Luís Vitório Cargnini
> Master Degree Student at PUC-RS on PPGCC - GAPH /
> www.inf.pucrs.br
> Computer Science Bacharelor
> PUC-RS
> Pontifícia Universidade Católica - Rio Grande do Sul
> Brasil
>
> ATTACHMENT part 2 application/pgp-signature
__________________________________
Do you Yahoo!?
Free Pop-Up Blocker - Get it now
http://companion.yahoo.com/
|
 |
Browse
