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    Navigation: All forums > Cores > Message List > Message Post

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    From: Luís Vitório Cargnini <cargnini@m...>
    Date: Thu, 27 Nov 2003 23:18:51 -0200
    Subject: Re: [oc] verilog or vhdl - Let's finish this discussion ?
    Top

    Vic nad tha other members,
    Excuse me but you are been to enthusiat whne you say that VHDL is only
    for geeks and Degree students and researchers.
    I work with both languages Verilog and VHDL. Memory is better to be made
    using Verilog, because synthesizers like Leonardo Spectrum see that the
    code defined is a memory and use the bit rams of a device if available,
    in VHSDl not ever this happens but in VHDL you could create more complex
    Structures like matrix of 12x12 (example only) std_logc_vectors(32 dowto
    0) so 12x12x32 and its a two dimensional matrrix now try to do this on
    Verilog is almost impossible. Verilog have only 17 nos synthesizable
    reserved words like fork and join ( i don't readed tha Verilog 2001
    specification yet, only in Quartus II ver 3.0 for example was added this
    kind of support), but VHDL has a bigger list of non synthesizable
    reserved words. 
    YES Verilog it's simple very simple, YES VHDL is more complex but not
    much more than Verilog, you only need to choose the best option for your
    project, entirely or some components of your projects. Finally the best
    langauage is that work, if Java did the work good (this was a little
    joke), try to get the best approach combinig the advance of two
    languages is the better so if Verilog is better to define memories, use
    Verilog for this, i fVHDL is better to define more complex strtuctures
    so use, don't close your horizons for only one language try use teh
    necessary tools to make your project in a adequate time, with adequate
    pricing.
    
    
    On Thu, 20 Nov 2003 09:01:19 -0800 (PST)
    Vic <vikrantps@y...> wrote:
    
    > HaHa, I agree with Paul to some extent...even I worked
    > on a 'medium' sized graduate project on VHDL in the
    > last 3 months. To be frank VHDL sucks!
    
    -- 
    Thanks && Regards
    Luís Vitório Cargnini
    Master Degree Student at PUC-RS on PPGCC - GAPH / www.inf.pucrs.br
    Computer Science Bacharelor
    PUC-RS
    Pontifícia Universidade Católica - Rio Grande do Sul
    Brasil
    

    PGP signature

    ReferenceAuthor
    RE: [oc] verilog or vhdlRedant Steven
    RE: [oc] verilog or vhdlVic

    Follow upAuthor
    Re: [oc] verilog or vhdl - Let's finish this discussion ?John Sheahan
    Re: [oc] verilog or vhdl - Let's finish this discussion ?Vic

     
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