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From: "Richard Herveille" <richard@a...>
Date: Tue, 25 Nov 2003 08:52:38 +0100
Subject: RE: [oc] verilog or vhdl

<snip>

> 
> That was the same primary goal of VHDL.
> 


<snip>

> 
> VHDL-AMS ? but there is a verilog counter part.
> 

So we agree both languages are (practically) equal(s).

Which one you use depends on your or your company's preference.

Can we end this war now????


Richard

Reference	Author
Re: [oc] verilog or vhdl	Nicolas Boulay