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Message
From: Tom Hawkins <tom@l...>
Date: Mon, 24 Nov 2003 07:51:26 -0600
Subject: Re: [oc] verilog or vhdl
On Monday 24 November 2003 03:33 am, Richard Herveille wrote:
> Sometimes ignorance is a blessing.
>
> I use both languages. Both have their advantage, both have their
> disadvantage.
>
> To me Verilog means a C-like environment and (most of the time)
> less typing.
> VHDL means a Pascal-like environment and more abstract structures.
> VHDL simply can do stuff Verilog can not, at least not yet.
>
> The new Verilog-2001 adds some of the nice features from VHDL. So
> barriers are fading and this discussion (which we have over and
> over again) becomes truly a holy war. Both languages do the job,
> both achieve good results, both have their followers.
>
> Truth is that VHDL originated from a US defense project and it is
> carrying around the bulk of government interference. Verilog
> originated from a small company (forgot its name) trying to build a
> 'higher' level (read higher than 'abel' and equivalents)
> synthesizable language. This company was later bought by Cadance,
> who included the tool/language in their development tools.
I believe the small company was Gateway Design Automation. I recently
met a few fellows that were part of Gateway and the original Verilog
project. I was surprised to learn that Verilog was originally
created as a simulation language -- the name Verilog is short for
"Verifying Logic". At that time synthesis was an afterthought and
didn't come along until years later. I wonder what Verilog would
look like today if it was originally designed for synthesis.
-Tom
>
> Oh and btw. There is an extension to VHDL that allows you to do
> true analog simulations. It's just that we (as DIGITAL) engineers
> never use it.
>
> I would stick with whatever your company (or your feeling) tells
> you to. There is no good and bad here. Only preferences and
> prejudices.
>
> Richard
>
--
Tom Hawkins
Launchbird Design Systems, Inc.
952-200-3790
http://www.launchbird.com/
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