|
Message
From: "Richard Herveille" <richard@a...>
Date: Mon, 24 Nov 2003 10:33:24 +0100
Subject: RE: [oc] verilog or vhdl
Sometimes ignorance is a blessing.
I use both languages. Both have their advantage, both have their
disadvantage.
To me Verilog means a C-like environment and (most of the time) less
typing.
VHDL means a Pascal-like environment and more abstract structures. VHDL
simply can do stuff Verilog can not, at least not yet.
The new Verilog-2001 adds some of the nice features from VHDL. So
barriers are fading and this discussion (which we have over and over
again) becomes truly a holy war. Both languages do the job, both achieve
good results, both have their followers.
Truth is that VHDL originated from a US defense project and it is
carrying around the bulk of government interference. Verilog originated
from a small company (forgot its name) trying to build a 'higher' level
(read higher than 'abel' and equivalents) synthesizable language. This
company was later bought by Cadance, who included the tool/language in
their development tools.
Oh and btw. There is an extension to VHDL that allows you to do true
analog simulations. It's just that we (as DIGITAL) engineers never use
it.
I would stick with whatever your company (or your feeling) tells you to.
There is no good and bad here. Only preferences and prejudices.
Richard
> -----Original Message-----
> From: owner-cores@o... [mailto:owner-cores@o...] On
> Behalf Of Vic
> Sent: Thursday, November 20, 2003 6:01 PM
> To: cores@o...
> Subject: RE: [oc] verilog or vhdl
>
> HaHa, I agree with Paul to some extent...even I worked
> on a 'medium' sized graduate project on VHDL in the
> last 3 months. To be frank VHDL sucks!
>
> I had worked on Verilog earlier and found the
> "Module-Testbench" structure of Verilog easier than
> VHDL. VHDL is totally digital (unlike Verilog/C like)
> so you have to be a MAJOR GEEK cos you have to
> remember all the individual signals (read 0's and
> 1's). Hey then what is the convenience of programming
> digital logic???
>
> Verilog is more commercial and popular according to
> me. Leave VHDL for geeky PhDs and for 'creating govt.
> jobs' for the defence sector. (It's much easier to
> fool the govt. into using VHDL instead of verilog)
>
> Vic.
>
> --- Redant Steven <redant@i...> wrote:
> > <?xml version="1.0" ?>
> > Damn. You unveiled my secret identity. I am Darth
> > Vader. I teach VHDL. :)
> >
> > Steven
> >
> > -----Original Message-----
> > From: paulcsouls@w...
> > [mailto:paulcsouls@w...]
> > Sent: Wednesday, November 19, 2003 17:02
> > To: cores@o...
> > Subject: RE: [oc] verilog or vhdl
> >
> >
> > Verilog and VHDL perform practically the same. The
> > choice of which to use is just a personal preference
> > linked to your personality type. Verilog users are
> > simple practical people. VHDL users are bad people.
> > This is because VHDL is evil. It has to do with its
> > derivation. Verilog is C like and C is used to
> > program normal stuff like computer games, word
> > processors and embedded programs in VCRs and alarm
> > clocks. VHDL is based on ADA. ADA is used by
> > bizarre PHDs lurking in the dark recesses of
> > universities and military bases working on
> > unspeakable research projects that would give Dr.
> > Frankenstein the willies. VHDL users say the VHDL is
> > more powerful than Verilog, but it is the power of
> > the dark side.
> >
> > Paul
> > (Its a joke, son. You missed it. I keep pitching em,
> > you keep missing 'em)
> >
> >
>
>
>
|
 |
Browse
