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Message
From: Vic <vikrantps@y...>
Date: Thu, 20 Nov 2003 09:01:19 -0800 (PST)
Subject: RE: [oc] verilog or vhdl
HaHa, I agree with Paul to some extent...even I worked
on a 'medium' sized graduate project on VHDL in the
last 3 months. To be frank VHDL sucks!
I had worked on Verilog earlier and found the
"Module-Testbench" structure of Verilog easier than
VHDL. VHDL is totally digital (unlike Verilog/C like)
so you have to be a MAJOR GEEK cos you have to
remember all the individual signals (read 0's and
1's). Hey then what is the convenience of programming
digital logic???
Verilog is more commercial and popular according to
me. Leave VHDL for geeky PhDs and for 'creating govt.
jobs' for the defence sector. (It's much easier to
fool the govt. into using VHDL instead of verilog)
Vic.
--- Redant Steven <redant@i...> wrote:
> <?xml version="1.0" ?>
> Damn. You unveiled my secret identity. I am Darth
> Vader. I teach VHDL. :)
>
> Steven
>
> -----Original Message-----
> From: paulcsouls@w...
> [mailto:paulcsouls@w...]
> Sent: Wednesday, November 19, 2003 17:02
> To: cores@o...
> Subject: RE: [oc] verilog or vhdl
>
>
> Verilog and VHDL perform practically the same. The
> choice of which to use is just a personal preference
> linked to your personality type. Verilog users are
> simple practical people. VHDL users are bad people.
> This is because VHDL is evil. It has to do with its
> derivation. Verilog is C like and C is used to
> program normal stuff like computer games, word
> processors and embedded programs in VCRs and alarm
> clocks. VHDL is based on ADA. ADA is used by
> bizarre PHDs lurking in the dark recesses of
> universities and military bases working on
> unspeakable research projects that would give Dr.
> Frankenstein the willies. VHDL users say the VHDL is
> more powerful than Verilog, but it is the power of
> the dark side.
>
> Paul
> (Its a joke, son. You missed it. I keep pitching em,
> you keep missing 'em)
>
>
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