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Message
From: Nicolas Boulay <nico@s...>
Date: Wed, 19 Nov 2003 23:05:20 +0000
Subject: Re: [oc] verilog or vhdl
Le Mercredi 19 Novembre 2003 07:52, joachim.strombergson@i... a
écrit :
> Aloha!
>
> Quoting nico@s...:
> > VHDL was firstly an IEEE standard for Dod, IMHO. Verilog was created by
> > Cadence before being an IEEE standard.
>
> VHDL was first a DoD standard for simulation. Verilog is *now* a standard.
> I.e. which language was first standardized is quite unimportant. What is
> important is which language is used the most *today* and possibly tomorrow,
> which language the EDA-vendors make money from, which market dominates etc.
>
> > No, they can't drop VHDL. Most code from EU are written in VHDL. That
> > can't be change so quickly.
>
> (1) Sure they can. Check out the ESNUG archives for the EDA-revenues break
> down in markets, FPGA vs ASIC and languge. The worldwide revenue for the
> EDA vendors is up in the 90% region for Verilog. It's basic strategic
> decision to keep or drop VHDL, drop that revenue but cut development cost
> and get more resources to other areas. Not an impossible decision at all.
>
http://www.deepchip.com/items/snug03-06.shtml
more than 60% of the market use mixed simulator.
> (2) Show statistics that most code from EU is writen in VHDL. ENSUG
> statistics and from market surveys says differently.
>
all the VHDL user that i know live in Europe :)
> (3) At least for ASICs, most developers use Verilog for GTL. This means
> that you have to support two languages in your tools, for example the
> simulator. If you can cut EDA-costs by conversion it *might* be enough of
> an incentive to ditch VHDL.
My company design ASIC in VHDL.
>
> > They would prefer to support only one langage instead of 2 but customers
> > didn't want to loose the use of there "internal" IP.
>
> Yes, there are companies like that, and the transition will take time. But
> for anyone using Synopsys tools (and Cadence etc) for a while it's quite
> obvious that the main development is for Verilog, and then for VHDL - that
> is, new features, fixes and development appears for Verilog first.
>
> The big thing that might change this is the trend towards FPGAs. VHDL is
> much more commonly used in FPGA development that in ASIC development. Also
> I would assume that there might be a market opening up to helt VHDL users
> to either convert their designs or provide other support to allow people to
> keep their VHDL IPs in VHDL.
>
> Note: This has nothing to do with technical merits between VHDL and
> Verilog. It's only about markets and money. Plain and simple.
>
I see that verilog run faster than vhdl, so we use verilog for gate level
simulation.
But at esnug, some people prefer vhdl simulator that behave mostly the same
in the opposite of verilog one.
> On a technical note the language shouldn't matter. And if it actually does,
> then can I have Superlog/SystemVerilog please. ;-)
Does it add something usefull ? I have heard that the complexity will be
finally better handle by managing IP, rather than having a hign level
langage. I have ever heard that some people want some place&route descriptive
information in the HDL code.
Nicolas Boulay
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