Verilog and
VHDL perform practically the same. The choice of which to use is just a
personal preference linked to your personality type. Verilog users are simple
practical people. VHDL users are bad people. This is because VHDL is evil. It
has to do with its derivation. Verilog is C like and C is used to program
normal stuff like computer games, word processors and embedded programs in
VCRs and alarm clocks. VHDL is based on ADA. ADA is used by bizarre PHDs
lurking in the dark recesses of universities and military bases working on
unspeakable research projects that would give Dr. Frankenstein the willies.
VHDL users say the VHDL is more powerful than Verilog, but it is the power of
the dark side.
Paul
(Its a joke,
son. You missed it. I keep pitching em, you keep missing 'em)
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