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Message
From: joachim.strombergson@I...
Date: Wed, 19 Nov 2003 08:52:47 +0100
Subject: RE: [oc] verilog or vhdl
Aloha!
Quoting nico@s...:
> VHDL was firstly an IEEE standard for Dod, IMHO. Verilog was created by
> Cadence before being an IEEE standard.
VHDL was first a DoD standard for simulation. Verilog is *now* a standard. I.e.
which language was first standardized is quite unimportant. What is important is
which language is used the most *today* and possibly tomorrow, which language
the EDA-vendors make money from, which market dominates etc.
> No, they can't drop VHDL. Most code from EU are written in VHDL. That
> can't be change so quickly.
(1) Sure they can. Check out the ESNUG archives for the EDA-revenues break down
in markets, FPGA vs ASIC and languge. The worldwide revenue for the EDA vendors
is up in the 90% region for Verilog. It's basic strategic decision to keep or
drop VHDL, drop that revenue but cut development cost and get more resources to
other areas. Not an impossible decision at all.
(2) Show statistics that most code from EU is writen in VHDL. ENSUG statistics
and from market surveys says differently.
(3) At least for ASICs, most developers use Verilog for GTL. This means that you
have to support two languages in your tools, for example the simulator. If you
can cut EDA-costs by conversion it *might* be enough of an incentive to ditch VHDL.
> They would prefer to support only one langage instead of 2 but customers
> didn't want to loose the use of there "internal" IP.
Yes, there are companies like that, and the transition will take time. But for
anyone using Synopsys tools (and Cadence etc) for a while it's quite obvious
that the main development is for Verilog, and then for VHDL - that is, new
features, fixes and development appears for Verilog first.
The big thing that might change this is the trend towards FPGAs. VHDL is much
more commonly used in FPGA development that in ASIC development. Also I would
assume that there might be a market opening up to helt VHDL users to either
convert their designs or provide other support to allow people to keep their
VHDL IPs in VHDL.
Note: This has nothing to do with technical merits between VHDL and Verilog.
It's only about markets and money. Plain and simple.
On a technical note the language shouldn't matter. And if it actually does, then
can I have Superlog/SystemVerilog please. ;-)
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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