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Message
From: nico@s...
Date: Tue, 18 Nov 2003 15:39:27 +0100 (CET)
Subject: RE: [oc] verilog or vhdl
> On Tue, 2003-11-18 at 17:41, Redant Steven wrote:
>> Ooops... are we going to hold a VHDL-Verilog war here? :)
>
> Hold, on I'm loading right now !
>
>> Choosing VHDL over Verilog because Verilog would be more of a standard
>> is not a good reason.
>
> Actually it is.
VHDL was firstly an IEEE standard for Dod, IMHO. Verilog was created by
Cadence before being an IEEE standard.
<...>
> Regards,
> rudi
> If focus is o design ASICs (not FPGAs) and plan on using Synopsys tools,
> Verilog is a good selection since Synopsys have decided to drop
> support for VHDL.
No, they can't drop VHDL. Most code from EU are written in VHDL. That
can't be change so quickly.
They would prefer to support only one langage instead of 2 but customers
didn't want to loose the use of there "internal" IP.
Nicolas Boulay
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