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From: joachim.strombergson@I...
Date: Tue, 18 Nov 2003 12:56:35 +0100
Subject: RE: [oc] verilog or vhdl

Aloha!

Quoting Redant Steven <redant@i...>:
> Ooops... are we going to hold a VHDL-Verilog war here? :)

Yes yes! ,-)

> Choosing VHDL over Verilog because Verilog would be more of a standard is not
> a good reason.

Actually, following an industry standard is usually a pretty good reason.
MS-Kerberos anyone? ;-)

If focus is o design ASICs (not FPGAs) and plan on using Synopsys tools, Verilog
is a good selection since Synopsys have decided to drop support for VHDL. 

Otherwise I agree with Redants suggestions.

-- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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Reference	Author
RE: [oc] verilog or vhdl	Redant Steven