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Message
From: "Redant Steven" <redant@i...>
Date: Tue, 18 Nov 2003 11:41:36 +0100
Subject: RE: [oc] verilog or vhdl
Ooops... are we going to hold a VHDL-Verilog war here? :)
Choosing VHDL over Verilog because Verilog would be more of a standard is not a good reason. VHDL has more power in test-bench writing, Verilog is more on the level of the hardware you want to achieve.
The quickest way to learn a hardware description language thoroughly is IMHO following a course.
You can also resort to books (lots of books have been mentioned in other people's mails on this list). As a VHDL teacher I have however experienced that no matter how many times you tell a classroom that they have to stick to the rules for synthesis (and you can check your code quite easily on these rules), there are always students that just write and push their code immediately into a synthesis tool. No simulation, no checking on the rules for synthesis.
If you start learning whichever of these languages you will GAIN time by in the beginning going through the (logical) steps one by one. Especially if you are learning things out of a book.
Write your code.
Check it for synthesizeability (for the parts you want to go to hardware)
SIMULATE IT!!!!!!!!!
then go into synthesis.
Learning a Hardware Description Language is understanding the simulation behaviour of the language. The Syntax is less important. Wich language you use is less important.
Steven
> -----Original Message-----
> From: harshit suri [mailto:suri_list@y...]
> Sent: Tuesday, November 18, 2003 09:49
> To: cores@o...
> Subject: [oc] verilog or vhdl
>
>
> hi i am a new
>
> I took a course in my undergrad on vhdl and in my
> design firm took a short course on verilog.both are
> NOT fresh in my memory at all. I wish to learn them
> and then start designing a DSP core under opencores. i
> know its already been designed. but i wish to do it
> anyway. i should be able to contribute larger and more
> useful designs later to the open cores community
> I am an electronics and commn engg as undergrad
> currently pursuing masters in EE
> pls advise should i start with vhdl or verilog. i feel
> like doing verilog as ive heard its the old industry
> standard.
> pls advise.
> I know my email could have been cut to one sentence.
> But i just wished to give some background
> thanks for your time
>
>
>
>
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