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Message
From: harshit suri <suri_list@y...>
Date: Tue, 18 Nov 2003 00:49:17 -0800 (PST)
Subject: [oc] verilog or vhdl
hi i am a new
I took a course in my undergrad on vhdl and in my
design firm took a short course on verilog.both are
NOT fresh in my memory at all. I wish to learn them
and then start designing a DSP core under opencores. i
know its already been designed. but i wish to do it
anyway. i should be able to contribute larger and more
useful designs later to the open cores community
I am an electronics and commn engg as undergrad
currently pursuing masters in EE
pls advise should i start with vhdl or verilog. i feel
like doing verilog as ive heard its the old industry
standard.
pls advise.
I know my email could have been cut to one sentence.
But i just wished to give some background
thanks for your time
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