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Message
From: antti@c...
Date: Mon, 17 Nov 2003 11:38:17 +0100
Subject: [oc] Opencores CAN core with XST 6.1
just for information:
the problem xilinx synthesis XST ver 5.2 had with Opencores CAN
are fixed in ISE 6.1 release so now CAN core can be synthesized
with xilinx implementation tools. there are no changes required
to CAN verilog RTL code.
Design Summary
--------------
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 622 out of 4,704 13%
Number of 4 input LUTs: 1,560 out of 4,704 33%
Logic Distribution:
Number of occupied Slices: 1,050 out of 2,352 44%
Number of Slices containing only related logic: 1,050 out of 1,050
100%
Number of Slices containing unrelated logic: 0 out of 1,050
0%
*See NOTES below for an explanation of the effects of unrelated
logic
Total Number 4 input LUTs: 1,605 out of 4,704 34%
Number used as logic: 1,560
Number used as a route-thru: 45
Number of bonded IOBs: 18 out of 142 12%
IOB Flip Flops: 19
Number of Block RAMs: 3 out of 14 21%
Number of GCLKs: 1 out of 4 25%
Number of GCLKIOBs: 1 out of 4 25%
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