|
Message
From: "Shehryar Shaheen" <shehryar.shaheen@u...>
Date: Sun, 16 Nov 2003 17:57:38 -0000
Subject: Re: [oc] DPLL using FPGA
Ammm read the mail archives
----- Original Message -----
From: <sandy_vallabh@y...>
To: <cores@o...>
Sent: Sunday, November 16, 2003 10:12 AM
Subject: [oc] DPLL using FPGA
> Hello,
> I am currently working on core design and i need Digital Phase Locked
> Loop (DPLL)implementation using VHDL. Can any body send me the DPLL
> code in VHDL??
>
> sandeep.
>
|
Browse
