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    Navigation: All forums > Cores > Message List > Message Post

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    From: Joachim Strömbergson<Joachim.Strombergson@I...>
    Date: Mon, 22 Sep 2003 13:21:16 +0200
    Subject: Re: [oc] 'malloc' on FPGA
    Top

    Aloha!
    
    antti@c... wrote:
    > I know all the target hardware that supports RTR
    > also software that is capable of that.
    
    Sure you know them all? ,-)
    
    > the software support for RTR is real real bad at the moment.
    > 
    > so a software tools that has better build in support for RTR
    > would be interesting at least if it really works.
    
    In my Master's Thesis (waay back) this was one of the issues we investigated. 
    What we saw was missing is a good abstraction/model of hardware in terms of 
    real-time. We tried to create a definition of real time-configuration and how 
    to describe hardware on a system level in terms of time domain changes.
    
    The system abstraction model of the hardware was the function call. A function 
    call was trapped by the underlying run-time system and the correct 
    FPGA-configuration was loaded and executed. Worked very nice, but since we 
    used old Xilinx 4x FPGAs, there were no partial reconfiguartion possible.
    
    The net result was that a "function call" had quite a bit of overhead, which 
    in turn means that the hardware granularity goes up (you want the hardware to 
    do lots of work so that you can amortize the cost of the overhead).
    
    I think that the old GARP project at Berkeley, the even older MIT Transit and 
    more recently the Chameleon processor are good examples of dynamic hardare 
    systems that supported real-time reconfig and had tools that made the system 
    model reasonable. Too bad Chameleon tanked.
    
    http://www.eetimes.com/story/OEG20010813S0079
    
    Another imho good solution was the "hardware beans" presented at DAC 1999. 
    Here is the paper:
    
    http://www.sigda.org/Archives/ProceedingArchives/Dac/Dac99/papers/1999/dac99/pdffiles/44_4.pdf
    
    I know Celoxica also have done some work using Handel-C both as a 
    HW-description language for the configurations and abstraction model for 
    reconfigurable HW.
    
    -- 
    Med vänlig hälsning, Yours
    
    Joachim Strömbergson - Alltid i harmonisk svängning.
    VP, Research & Development
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    InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÖTEBORG / Sweden
    Tel: +46 31 68 54 90  Fax: +46 31 68 54 91  Mobile: +46 733 75 97 02
    E-mail: joachim.strombergson@i...  Home: www.informasic.com
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    ReferenceAuthor
    Re: [oc] 'malloc' on FPGAAntti

    Follow upAuthor
    Re: [oc] 'malloc' on FPGANicolas Boulay

     
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