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Message
From: Rudolf Usselmann <rudi@a...>
Date: 20 Sep 2003 11:24:13 +0700
Subject: Re: [oc] FREE Verilog Simulator
On Fri, 2003-09-19 at 20:42, Joachim Strömbergson wrote:
> Aloha!
>
> Rudolf Usselmann wrote:
> > I just stumbled across this baby:
> >
> > http://www.pragmatic-c.com/gpl-cver/
>
> Pretty kewl. I compiled and built it without any problems. Kudos to the
> Pragmatic-C team to produce a nice tarball with lots of READMEs explaining all
> directories etc.
>
> I've done som initial testruns on it works. What I'm curious/concerned about
> is simulation speed, especially on non-trivial designs. Icarus Verilog is in
> my opinion quite good in this respect. If time permits I'll try and do a
> shootout between these two Open Source Verilog simulators.
Hi !
I must say I find cver much more stable and faster than
icarus. So far I have found only one bug in it and the
authors immediately fixed it (there is a new release as
of last night).
Here are my test numbers, please add your as well, so we
get a more broader spectrum of test results.
Simulation of a Small verilog block. Run 2 is 10x more test
vectors than Run 1
Run 1 Run 2
ncsim 1.87 5.64 sec
cver 4.54 43.04 sec (about 4-5 times faster than icarus)
icarus 17.92 217.41 sec
Same as above, except the DUT has been synthesized to a 0.18u
ibrary. This is a Gate Level simulation now ....
Run 1 Run 2
ncsim 9.66 21.22 sec
cver 12.90 90.48 sec
icarus [Reports "error: syntax error in specify block"]
Of course these are not complete comparisons and your mileage
will vary. However it give you a rough indication what to expect ...
I'm definitely glad that we have both !
Cheers !
rudi
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