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Message
From: Marko Mlinar <markom@o...>
Date: Mon, 15 Sep 2003 16:26:56 +0200
Subject: Re: [oc] KRPAN: OC embbedded FPGA project [verilog2bitstream]
On Monday 15 September 2003 13:12, antti@c... wrote:
> Hi Marko,
>
> yes, I found that too, the MAP PLACE and ROUTE all do work !!
> and it is pretty nicely 'visualized' so you can see it.
>
> FYI the KRPAN is very close to CAL1024 (algotronix) CAL had
> not 8 to 1 but 4 to 1 muxes and only neighbor connections.
> (and simpler function block)
>
> Question: could you please please add 2 things to KRPAN
> (in minimal functionality)
>
> 1 IO pin locking
> 2 support for custom sizes of array, eg 8 x 8 GPC's
>
> ? I think it would no be too hard (for the authors at least)
> as said KRPAN GPC is approx 26 slices so it is reasonable small
> to be implemented in exisiting FPGAs.
>
> if [1] and [2] from above are done then it is possible to make
> a real working FPGA prototype.
>
> the 18 by 18 array would not fit into medium size FPGAs so
> I cant use the original KRPAN without modifications.
Antti,
The above functionality is already supported by the flow, however there is no
UI to enter it. I don't know if KRAPN is directly useful for you, I just
wanted to let you know. You are of course free to copy and modify the code
for your project.
Otherwise I cannot join your project, since I am loaded with work at my job
and am I also working on other OC projects, I wish to finish first.
best regards,
Marko
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