|
Message
From: Marko Mlinar <markom@o...>
Date: Mon, 15 Sep 2003 10:53:29 +0200
Subject: Re: [oc] KRPAN: OC embbedded FPGA project [verilog2bitstream]
Antti,
Yes, KRPAN project started at least 2 years ago from now. I didn't know any
HDL then, but still I was hoping someone would write HDL model.
For efficient FPGAs have to have custom desing and quite favorably custom FAB
process ;) I guessed it was kinda too much for that time ;)
Besides parser I think M&P&R tool should work nice. Code is also quite clean.
Marko
On Friday 12 September 2003 16:52, antti@c... wrote:
> KRPAN seems to be sleeping?
> just looked again at KRPAN place and route and it seems todo
> something - well I only tested with very simple verilog designs.
>
> there was PROJECT HELP NEEDED - just for information for testing
> I implemented GPC cell for Virtex (incl programming interface) it
> takes 26 slices, so a small KRPAN array (8 x 8 GPC array) should
> fit into medium size Virtex. So if only adding constraints to KRPAN
> software it would be useable in real silicon :)
>
> antti
|
 |
Browse
