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From: joachim.strombergson@I...
Date: Wed, 27 Aug 2003 13:03:38 +0200
Subject: RE: [oc] Encryption algorithms map to hardware

Aloha!

Quoting Deepu C John <deepu@u...>:
> 
> > Hmm, unless you can find a mathematical relationship between
> > the input and output, which will be more efficient than a look
> > up table (ROM), there is no advantage in implementing it any
> > other way.
> 
> GATE SIZE of the SBOX will be lesser anyway... But Implementing  Galois
> field multiplication in HW will be complex  
> Will be suitable for very compact implementations 

What? GF-mult in AES == XOR. Unless you are using old-school FPGAs whith bad
support for XOR-structures, you will have no problems.

I don't recommend a Shannon expansion representation though.
-- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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Reference	Author
RE: [oc] Encryption algorithms map to hardware	Deepu C John