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Message
From: frank.baier@g...
Date: Sun, 27 Jul 2003 23:11:03 +0200
Subject: Re: [oc] VHDL Problem
----- Original Message -----
From: "Matija Habek" <mhabek@n... >
To: cores@o...
Date: Wed, 9 Jul 2003 23:55:00 +0200
Subject: [oc] VHDL Problem
>
>
> Can I simulate a pull-up resistor in VHDL using Graphic Editor and
> how?
>
> --
> Besplatni e-mail - http://webmail.iskon.hr/
>
Hi !
What is the name from the graphic editor ?
If you want to simulate a resistor you should use vhdl-ams, but it's
possible to program the behaviour for a pull up in vhdl for simulation.
best regards,
Frank
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