LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: "Richard Herveille" <richard@a...>
    Date: Wed, 23 Jul 2003 20:32:10 +0200
    Subject: RE: [oc] I2C core in VHDL
    Top

    
    
    Master or slave ????
    
    Check the opencores i2c project for a i2c master core (in verilog AND
    vhdl).
    
    Richard
    
    
    > -----Original Message-----
    > From: owner-cores@o... 
    > [mailto:owner-cores@o...] On Behalf Of 
    > duboisjulien15@h...
    > Sent: woensdag 23 juli 2003 16:38
    > To: cores@o...
    > Subject: [oc] I2C core in VHDL
    > 
    > 
    > 
    > 
    > Hello everybody,
    > 
    >  I am looking for free I2C core in VHDL. Anybody who can help me, 
    > please send me an email...
    > 
    > Thanks
    > 
    > 
    > 
    
    
    
    

    ReferenceAuthor
    [oc] I2C core in VHDLDuboisjulien15

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.