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Message
From: spyros <spyros_s@f...>
Date: Fri, 18 Jul 2003 19:27:10 +0300
Subject: Re: [oc] for more details information
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"???????????????????????????" wrote:
> Hello,
>
> This is Lucy from China. I am very interested in the EPP IPcore at
www.opencores.org. This site said that the FSM diagram and its module is
given on 25/4/2003, but I could not find them. I have some questions
about this IP core and can't contact with the project maintainer Malik
Ahmad Yar Khan. Would you mind helping me?
>
> Thanks and regards
>
> Lucy Qu
> Changsha, Hunan, China
>
>
> ______
> ===================================================================
>
>
hi,
i'm not sure about it but i found this in opencores:
(that's verilog, isn't it?)
- ---cut here--
//below is the code for EPP module .
module epp_port (send_info,sent_info,write,data_strobe,resetport,
addr_strobe, interrupt,wait_sig,
spare1,recieved_info,
data_send_reg,addr_send_reg,
data_store_reg,
addr_store_reg,spare2,spare3,
data,reset,clock,oe,spare4,testwaitin,testwaitout
);
output testwaitin;
output testwaitout;
input[1:0] send_info;
output[1:0] sent_info;
input spare4;
output oe;
inout[7:0] data;
input[7:0] data_send_reg;
input[7:0] addr_send_reg;
output[7:0] data_store_reg;
output[7:0] addr_store_reg;
output[1:0] recieved_info;
// input data_
input write;
input data_strobe;
input resetport;
input addr_strobe;
output interrupt;
output wait_sig;
output spare1;
output spare2;
output spare3;
input reset;
input clock;
reg[1:0] sent_info;
reg interrupt;
reg wait_sig;
reg spare1;
reg spare2;
reg spare3;
// reg data_out;
reg[2:0] state;
//new entry
reg[7:0] data_send_reg1;
reg[7:0] addr_send_reg1;
reg[1:0] recieved_info;
reg[7:0] data_store_reg;
reg[7:0] addr_store_reg;
// reg data_send_reg;
// reg addr_send_reg;
// reg[5:0] counter;
parameter s1=3'b000;
parameter s2=3'b001;
parameter s3=3'b010;
parameter s4=3'b011;
parameter s5=3'b100;
parameter s6=3'b101;
parameter s7=3'b110;
parameter s8=3'b111;
//using spare1=0 to send data & using spare1=1 to send address
/*
inout[1:0] send_info;
inout[7:0] data;
*/
reg[1:0] set;
reg[7:0] data_value;
assign oe=(set[0] | set[1]);
assign data[0]=(set==2'b00) ? 1'bz : data_value[0];
assign data[1]=(set==2'b00) ? 1'bz : data_value[1];
assign data[2]=(set==2'b00) ? 1'bz : data_value[2];
assign data[3]=(set==2'b00) ? 1'bz : data_value[3];
assign data[4]=(set==2'b00) ? 1'bz : data_value[4];
assign data[5]=(set==2'b00) ? 1'bz : data_value[5];
assign data[6]=(set==2'b00) ? 1'bz : data_value[6];
assign data[7]=(set==2'b00) ? 1'bz : data_value[7];
reg testwaitin,testwaitout;
always@(posedge clock or posedge reset)begin
if(reset)
begin
testwaitin<=1'b0;
testwaitout<=1'b0;
set<=2'b00;
interrupt<=1'b0;
wait_sig<=1'b0;
spare1<=1'b0;
spare2<=1'b0;
spare3<=1'b0;
state<=3'b000;
recieved_info<=2'b00;
sent_info<=2'b00;
data_value<=8'b11111111;
data_store_reg<=8'd255;
addr_store_reg<=8'd255;
end //end of if (reset statement
else
begin
if(sent_info==2'b00)
begin
// interrupt<=1'b0;
sent_info<=send_info;
spare1<=1'b0;
spare2<=1'b0;
// spare3<=1'b0;
end
else if(sent_info==2'b01)
begin
//interrupt<=1'b1;
spare1<=1'b1; //i.e to send data
spare2<=1'b0;
// spare3<=1'b0;
data_send_reg1[7:0]<=data_send_reg[7:0];
end
else if(sent_info==2'b10)
begin
// interrupt<=1'b1;
spare1<=1'b0; //i.e to send addr
spare2<=1'b1;
// spare3<=1'b0;
addr_send_reg1[7:0]<=addr_send_reg[7:0];
end
else begin
// interrupt<=1'b1;
// spare1<=1'b1; //i.e to send addr & data respectively
data_send_reg1[7:0]<=data_send_reg[7:0];
addr_send_reg1[7:0]<=addr_send_reg[7:0];
spare1<=1'b1;
spare2<=1'b1;
// spare3<=1'b0
// interrupt<=1'b0;
end
if(spare4==1'b0)begin spare3<=1'b0; recieved_info<=2'b00; end
case(state)
3'b000: //neutral state
begin
if(resetport==1'b0)begin
set<=2'b00;
sent_info<=2'b00;
recieved_info<=2'b00;
interrupt<=1'b0;
wait_sig<=1'b0;
spare1<=1'b0;
spare2<=1'b0;
spare3<=1'b0;
state<=3'b000;
data_value<=8'b00000000;
end
else begin
if( data_strobe==1'b0 || addr_strobe==1'b0)
begin
if(data_strobe==1'b0)
begin
if(write==1'b0)begin
state<=3'b001; //go to read data state
spare3<=1'b1;
end
else begin
state<=3'b010; //go to write data state
spare1<=1'b0;
spare2<=1'b0;
// data_value[7:0]<=data_send_reg[7:0];
// set<=2'b01;
// set<=2'b01;
// sent_info<=2'b01;
end
end
else begin
if(write==1'b0)begin
state<=3'b011; //go to read address state
spare3<=1'b1;
end
else begin
state<=3'b100; //go to write address state
spare1<=1'b0;
spare2<=1'b0;
// data_value[7:0]<=addr_send_reg[7:0];
// set<=2'b10;
// sent_info<=2'b10;
end
end
end
else
state<=s1;
end
end
3'b001: //reading data state
begin
if(data_strobe==1'b0)
begin
testwaitin<=~testwaitin;
wait_sig<=1'b1;
state<=3'b001;
data_store_reg[7:0]<=data[7:0];
end
else
begin
recieved_info<=2'b01; //recieved data
wait_sig<=1'b0;
state<=s1;
end
end
3'b010: //write data state
begin
if(data_strobe==1'b0)begin
data_value[7:0]<=data_send_reg1[7:0];
set<=2'b01;
wait_sig<=1'b1;
sent_info<=2'b00;
end
else
begin
wait_sig<=1'b0;
set<=2'b00;
state<=s1;
end
end
3'b011: //reading address data
begin
if(addr_strobe==1'b0)begin
wait_sig<=1'b1;
addr_store_reg[7:0]<=data[7:0];
// spare3<=1'b1;
end
else
begin
testwaitout<=testwaitout;
recieved_info<=2'b10;
wait_sig<=1'b0;
state<=s1;
end
end
3'b100://writing address data
begin
if(addr_strobe==1'b0)begin
data_value[7:0]<=addr_send_reg1[7:0];
set<=2'b10;
wait_sig<=1'b1;
if(spare2==1'b1 && spare1==1'b1)
sent_info<=sent_info;
else sent_info<=2'b00;
end
else
begin
wait_sig<=1'b0;
set<=2'b00;
state<=s1;
end
end
endcase
end //enf of the else of if(reset) statement
end //end of always statement
endmodule
- --cut here--
i found it in the following url:
http://www.opencores.org/projects/epp/epp1.9
i think that's what the author has to offer.
Hope this helped!
- --spyros
- --
öïéôçôÞò óôï Ä.Ð.È
student @ DUTH
public key: dalab.ee.duth.gr/~spyros/my_pub.asc
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--
φοιτητής στο Δ.Π.Θ
student @ DUTH
public key: dalab.ee.duth.gr/~spyros/my_pub.asc
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