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From: bob@d...
Date: Mon, 14 Jul 2003 16:20:26 -0100
Subject: [oc] CAN Core Questions

Igor,

I've spent a litttle time looking over the CAN core and have some 
questions.

1.  Is the CAN core modeled after any existing CAN device or IP (i.e. any 
intended software/functional compatability)?

2.  Is any further documentation (i.e. theory of operation, register file 
definition/programmer's guide) available?

3.  I understand the the OpenCores CAN is being validated against the 
Bosch VHDL reference model.  Is there a timeframe for the completion of 
the validation?

4.  I see from the latest verilog code that several changes have been 
made that are not reflected in the VHDL code base.  Is there a 
timeframe for the incorporation of changes to the VHDL model and 
validation of the VHDL model?

thanks,
bob