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Message
From: "Jerzy G" <furia1024@w...>
Date: Fri, 20 Jun 2003 12:06:43 +0200
Subject: Odp: [oc] vhdl question
Hello
> start <= '1' when read='1' and addr(7 downto 0)="11111111"
else '0';
>
> Now what happens here is that read goes high only for one
clock cycle and hence so does start. How can I make start stay
high for 2 or more clock cycles and then go low ?
There are some solves, one of them is:
use FF and OR input and output.
Example:
-----------------------------------------------
start <= '1' when read='1' and addr(7 downto 0)="11111111"
else '0';
P1: process(CLK)
begin
if (CLK'event and CLK = '1') then
start_1 <= start;
end if;
end process;
-- here is 2 clks wide signal:
start_2 <= start OR start_1;
-------------------------------------------------
If You want wider, use more FFs and OR all outputs and input.
Jerzy Gbur
--
"Everything is simple until it'll be comprehensible" - furia
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