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Message
From: John Sheahan <jrsheahan@o...>
Date: 20 Jun 2003 08:45:39 +1000
Subject: Re: [oc] interfacing 16Mhz and I Mhz clock registers
On Fri, 2003-06-20 at 02:34, Umair Farooq Siddiqi wrote:
> I can adjust skew between two clocks, at present there is no skew between them, 1 Mhz Clock can be considered as 16Mhz clock divided by 16.
>
> Thanks
(its early and my coffee is not working yet. please think thru these
points)
Sounds like the clocks are synchronous then - which simplifies things a
lot. Otherwise memories and junk may be required.
If the 16M and the 1M are exactly in phase, there is no issue - you can
connect them directly q -> D
(I assume the min clock ->Q delay plus any interconnect delay is more
than the hold time.
If this is wrong, shift registers dont work either)
If the 1M clock is slightly advanced on the 16M, even more margin.
With reasonable clock control, this is probably where you want to be.
If the 1M clock is delayed WRT the 16M - timing can get nasty.
And this is the common case when 1M is just divided from 16M.
Then a delay in all 16 datapaths longet than the clock skew is probably
the required solution, which is implemntation specific and slightly
backend nasty.
all of these delays I hope are a tiny fraction of a 16mhz clock period.
john
>
>
> John Sheahan <jrsheahan@o...> wrote:
> On Thu, 2003-06-19 at 19:42, Umair Farooq Siddiqi wrote:
> >
> > Hi
> >
> > I am interfacing two 16-bit wide registers, one running at 16 Mhz to another register running at 1 Mhz. On 16 Mhz side though the clock is at 16 Mhz but data only changes after 16 clocks, hence I am thinking of directly connecting both clock frequency registers. Would you kindly suggest me whether my approach is correct or not? Is there any special care required to meet setup and hold timings ?
> >
> whats the skew between the 16MHz nd the 1MHz clocks?
>
>
>
>
>
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