Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: ritika_dua@y...
Date: Mon, 16 Jun 2003 11:11:03 -0100
Subject: Re: [oc] constraints while programming in VHDL

sir, i want to know how we can use delays in the vhdl code, as the 
delays can't be synthesized .

Follow up	Author
Re: [oc] constraints while programming in VHDL	John Sheahan
Re: [oc] constraints while programming in VHDL	Uwe Bonnes