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Message
From: <nico@s...>
Date: Fri, 13 Jun 2003 17:46:11 +0200 (CEST)
Subject: [oc] The use of both edge of the clock.
At school, we learn that design must be full synchronous on one edge of
the clock to avoid any timing hasard.
But, i see very often some chip interface that sample or deliver the data
at the folling edge of the clock. Does this trick very usefull ? Does it
generate dozen of "false path" for synthetiser ?
What is the common rules and pitfall about using this ?
nicO
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