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Message
From: manxi wang <wangmanxi@y...>
Date: Wed, 16 Apr 2003 01:37:39 +0100 (BST)
Subject: Re: [oc] async/sync reset.
well
--- cyrano@n... wrote: > Joachim Strömbergson
> <Joachim.Strombergson@I...> a écrit :
>
> > Aloha!
> >
> > cyrano@n...
> > wrote:
> > > :) Funny. It's seems that it is another
> religious war. In the lab where i
> > work, sync reset are forbiden.
> >
> > Yes it most certainly is. A war that just recently
> erupted, see:
> >
> > http://www.deepchip.com/items/0396-01.shtml
> > http://www.eetimes.com/story/OEG20030401S0052
> >
> > Rudis reference to Cliff Cummings paper is a good
> suggestion.
> >
> > The trend for high-end VDSM-technologies (90nm and
> downwards) seems to be
> > towards synch resets.
> >
>
> One things is bizard : sync reset could make meta
> stability, because you can't say that the release or
> the setting of the reset will not happen at edge of
> the clock. In case of async reset, i can't imagine
> than a metastability could arrive at release because
> all state are stable waiting for the next clock edge
> (between reset and release of reset, no signal
> change, so no glitch appear when the clock egde
> arrive).
>
> Nicolas Boulay
>
> > --
> > Med vänlig hälsning, Yours
> >
> > Joachim Strömbergson - Alltid i harmonisk
> svängning.
> > VP, Research & Development
> >
>
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> > E-mail: joachim.strombergson@i...
> > Home: www.informasic.com
> >
>
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> >
> >
> >
>
>
>
> ___________________________________
> Webmail Nerim, http://www.nerim.net/
>
>
>
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