LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: "Nanda Kumar K.G" <nanda@c...>
    Date: Thu, 13 Jul 2000 20:33:05 +0500 (GMT+0500)
    Subject: Re: [oc] new
    Top
    I would like to be a part of your org.
    I am interested in working on core simulation using VHDL
    I am currently doing my masters in Electronics with VLSI as one of
    the courses. I would like to work in this field as my project.
    Kindly send me information about certain projects
    which I could complete by December which is the deadline for
    my course completion.
    My name is
    Ms. P.Vani Prasad
     
    you could contact me at

    ReferenceAuthor
    [oc] newMasterm

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.