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Message
From: johnp at probo.com<johnp@p...>
Date: Fri Jan 13 23:00:58 CET 2006
Subject: [usb] More USB 2.0 core problems..., one fake problem...
My original post discussed a problem with corrupt SRAM data if
writes to ram happened concurrently with read requests. The
problem turns out to have been in my sync SRAM model.
John Providenza
----- Original Message -----
From: johnp at probo.com<johnp@p...>
To:
Date: Thu Dec 29 23:19:54 CET 2005
Subject: [usb] More USB 2.0 core problems...
> It looks like there may be two more problems in the USB 2.0 core
> controller.
> 1) An IN pkt issued to an empty BULK endpoint causes bad things to
> happen. The DMA tries to fetch data, but since the counter is at 0,
> it wraps to a big number and the DMA tries to send LOTS of data
> back
> to the host.
> 2) If the Wishbone interface is writing to the SRAM buffer while an
> IN
> packet is being processed, the data being sent to the host can be
> corrupted. The data pipeling in the usbf_idma.v is note quite
> correct.
> Is anybody doing any maintenance on the core at this point?
> John Providenza
>
>
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