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From: dmarris@c...<dmarris@c...>
Date: Fri Oct 8 16:09:57 CEST 2004
Subject: [usb] usb1.1 Simulation
----- Original Message -----
From: M. AbuKhater<perocletos@y...>
To:
Date: Sun May 9 13:43:27 CEST 2004
Subject: [usb] usb1.1 Simulation

> Hi all
> I was trying to do some simulation on the USB1.1 core design, it
> has its own test bench verilogs. am using the Model sim, but it
> seems not working properly.
> has any one tried to do simulation on this core, whats the right
> procedure for that ?
>
> Abukhater
>

Abukhater,

I have just started simulating the USB 1.1 core with ModelSim and it
seems to be working properly. Being new to USB, I cannot guarantee
the results, but none of the error messages have appeared and the
signals are toggling. Have you gotten any further since your post
on May 9?

Regards,
Dalton