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Message
From: nocm@g...<nocm@g...>
Date: Tue May 11 10:51:41 CEST 2004
Subject: [usb] USB Core in VHDL and Testbench
Hi!
For my study I need the USB core in VHDL.
I had translated the Verilog into VHDL with X-HDL and I also could
synthesize it. Only with the writing of a testbench I have some
problems, because I am don't know how exactly.
Perhaps someone has a functioning VHDL variant with a testbench,
which would help me much.
Thank you
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