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Message
From: Rick Collins<opencores.usb@a...>
Date: Fri Mar 5 17:44:13 CET 2004
Subject: [usb] Suspend mode and FPGA:s
At 11:17 AM 3/5/2004, you wrote:
>first of all thanks for the quick reply
>
>The info you gave me is very usefull, i know now i wont be able to
>implement suspend/resume.
>i will have to be working on an xilinx virtex II 8000. Though that's not
>that big of a punishment :-), it draws too much power.
That is a really large part. I will be surprised if you could get that to
run off the USB power anyway since it is limited to 2.5 Watts. If you are
using half of this FPGA and running it at much speed, it will use more than
this easily.
>i think i'm gonna NOT suspend my device at all (though not up to spec)
>since it isn't powered by the usb bus. (for a quick reference to my
>project (if you're interested) see the bumped post i did couple of days
>ago). If i wont suspend it, it'll respond to resume signaling nonetheless
>since my core's still up and running...right?
I don't know the USB spec, but it should work ok. I looked at your post
and I don't see where you ever got a response. Did you get the interface
issue straightened out?
>i'll have to check whether it is at all possible to not suspend a device,
>though in my case i think there aren't too many other options.
>
>quote
> > What exactly is the wake up criteria in the USB spec? It would be
> > an
> > unusual circuit that could do significant processing and still have
> > very
> > low power like this (500 uA). But then I guess it is not
> > impossible. Does
> > the circuit wake up on the first signal transition on the USB bus?
>unquote
>
>i think i wont be able to implement the suspend mode because of this
>too, since even when the phy wakes up on the first signal transition, my
>DCM in the FPGA will still need time to lock.
>
>i just found out my phy isn't bus powered too so not suspending the
>device wont be a problem i guess...
I am sure the spec allows for devices that don't actually power down if
they are not on USB power. A printer is a good example, they don't power
down at all other than when *they* decide to. Even then I am sure they are
really powered up still, just the motors are off.
I am pretty sure the suspend state is intended to be done by custom chips
where you can control power much more easily.
We are designing a new DSP board which uses an FPGA and daughter cards to
add IO capability. I belive the USB2.0 core you are looking at is a slave
only. We would like to implement a master/slave device, likely OTG, using
the FPGA and a PHY like you are doing. Any ideas on how to do this? Do
you know of anyone working on a USB 2.0 (high speed) OTG core? I have not
found any ASSP chips for this either. All the OTG chips seem to be full
speed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
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