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Message
From: Rudolf Usselmann<rudi@a...>
Date: Sat Jan 10 16:50:57 CET 2004
Subject: [usb] USB2.0
On Sat, 2004-01-10 at 18:23, Mohammad AK wrote:
>
> 1. where can I find this FIFO , which .v file?
> 2. when I added the sources to the USB project it the hierarchy did
> not start only with usbf_top.v , the highest files were also the
> premitives.v and the usb_defines.v, and the synthesizer did
Hmm, there should NOT be a "primitives.v" file. You can
ignore that if it is in the CVS - it should'n be ...
The "usb_defines.v" is an include file. All you have to
do is to tell your synthesis tool where include files
are located and it should work just fine.
> not see the usb_defines, so I had to copy it's contents to the rest
> of the files ( *.v ) , and it worked perfectly but -as mentioned
> before - needs at least 200K FPGAs .
> I wanted to know whether this is the correct way of doing this
> synthesizing. besides minimizing the design more !
To "optimize" the design, you should very carefully read
the usb_defines.v and the included documentation. There
are no FIFOs used in the design (actually one, and it's
already set to the absolute minimum (4 entries deep).
Certainly reducing the memory size and number of endpoints
will make it smaller. Getting a hold of a decent synthesis
tool should help as well.
The USB 2.0 function is about 20K ASIC (std. cell) gates.
Typical ratio of FPGA to ASIC gates ranges in the 4-8
FPGA gates for each ASIC gate. So the numbers you are
getting are about 20% higher than I would expect.
You should also make sure you know exactly how to use
your synthesis tool (trust me that is the case in 90%
of all 'bad' results). Make sure the memory is
constructed of BlockRams and NOT Flops or LUTs.
Regards,
rudi
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