|
Message
From: Ash <anangia@m...>
Date: Wed, 29 Oct 2003 02:49:50 +0100
Subject: [usb] usb1_core EndPoint I/O question
Hi All
Firstly I have written my own top entity file and instantiated usb1_core
(which includes usb_phy) as a component. I work in VHDL and thus the
need to ask the following question.
1.
I was just assigning all the signals for all the I/O's of usb1_core. Looking
at Rudi's test bench verilog file (test_bench_top.v), he's done the
following:
// End point 1 configuration
.ep1_cfg( `ISO | `IN | 14'd0256 ),
This is fine in verilog, however how do I do this in the case of VHDL. I'm
interested in `BULK | `OUT | 14'd064. I mean how do I represent this in
bits "xxxxxxxxxxxxx"? (PS: correct me if i'm wrong but OUT is receving
stuff from PC right?)
2.
Also am the value of epN_empty and epN_full will depend on whether I
set epN_cfg as IN or OUT.. Am I right?
3.
I can't figure out what these signals do?
epN_bf_en and epN_bf_size
4.
Lastly all connections for vendor signals are out. only one is in which is
vendor_data. I have ignored the out signals, but assigned a 16-bit value
to vendor_data. my question is why is there no place for product id?
Thanks a lot guys
Ash :)
|
 |
Browse
