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Message
From: "Marc Reinig" <mreinig@p...>
Date: Mon, 27 Oct 2003 12:11:23 -0800
Subject: RE: [usb] USB 1.1 PHY, DPLL question
> -----Original Message-----
> From: owner-usb@o... [mailto:owner-
> Subject: RE: [usb] USB 1.1 PHY, DPLL question
>
> ----- Original Message -----
> From: "Marc Reinig" <mreinig@p... >
> Subject: RE: [usb] USB 1.1 PHY, DPLL question
> >
> > I don't know why you think that +/- 20% are possible.
>
> just happened to read datasheet for ISP1181 there is stated
> that SE0 (during normal transmittion!) as seen on the single
> ended receivers can be as much as 14ns,
You don't quote anything but the number (14) so it is difficult to tell what
you are talking about. However, I assume you are referring to tFST.
> 1 bit is 83 ns, that makes up to 17% error if looking
> at single ended receivers!
>
> (this is time during normal transition where single ended
> receivers may see SE0 state on the bus - this SE0
> is seen at every transition of the incoming signal)
>
> thats what one manufacturer says, this number: 14 ns
> may differer a little depenig on the manufacturing technology, etc.
No. This is not one manufacturer's number. This is straight out of the USB
spec. The value cannot be larger than 14 nSec., period. In addition, it
has little directly to do with jitter in the data lines.
tFST has to do with making sure that despite all the delays that can happen
in a system, not just limited to jitter, if will not recognize a combination
of D+ and D- both less than Vih as a SE0 if it is not at least 14 nSec long.
This is not a jitter spec, and in any case the MAX it can be is 14.
> nut my dumb estimate up to 20% is not so impossible at all.
It's not a dumb estimate it's just not based on understanding a complex spec
well enough.
Marc Reinig
System Solutions
Windows Driver and Embedded Product Consulting
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