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Message
From: antti@c...
Date: Sat, 25 Oct 2003 16:33:54 +0200
Subject: RE: [usb] USB 1.1 PHY, DPLL question
> I don't know why you think that +/- 20% are possible.
>
> In an IC design, part of the designers job is to match performance
> of circuits that need to be held to certain tolerances. On a give
> die, the
> performance characteristics of the transistors are going to match
> very closely. The total capacitive load is harder to balance, but,
> after all, that's what they get paid for.
>
> Marc Reinig
> System Solutions
there are different types of input receivers separate for
single ended and differential signals.
the output of the differential receiver defenetly switches
at different time than the single end receivers.
I dont see some one could argue here.
The actual difference between the edges on the single
ended receivers and differential receiver well this could be
matter of discussion, but what I have seen in the case of
USB tranceiver, I wouldnt be surprised in values of 20%
at 48MHz sampling clock the same bit seen by
differential receiver 4 bits
single ended receiver 2 bits !!
same bit sampled from different receiver outputs (RCV vs DP/DM)
the above behaviour can be observed. I do believe my eyes.
if the single ended receivers would not have 'jitter' then then
the signal bit widths could not differ so much.
thats why USB uses differential signalling what is way more
reliable as single ended transmittion.
antti
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