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Message
From: antti@c...
Date: Fri, 24 Oct 2003 20:31:52 +0200
Subject: Re: [usb] USB 1.1 PHY, DPLL question
> On Fri, 2003-10-24 at 19:52, antti@c... wrote:
> > Hi Rudolf,
> >
> > assign change = (rxdp_s0 != rxdp_s1) | (rxdn_s0 != rxdn_s1);
> >
> > the above is used in DPLL but DP and DM signals are inputs
> > from single ended reicevers and have totally different
> tresholds
> > as the differential receiver (e.g. RCV pin on tranceiver
> chip).
> >
> > if you look with scope or logic analyzer then the bit widths
> on
> > DP and DM may be wrong as much as 40% percent relative to
> > real bit width that under the conditions where RCV signal
> exposes
> > correct bit widths (due to different receiver treshold).
>
> 40% error ?! That sounds like a lot.
its a dumb estimate not on edge jitter but bit 'width' jitter
> > the 'change' signal is be '1' during any change on DP or DM,
> > but those changes are not always at the same time.
> > They should be but with real devices they are not.
> > Te signals on DP DM may be actually visually so bad that
> > one wonders why is the signal still received ok.
> > Well the RCV signal is usually OK
> > (if not then of course data transmittion fails already).
> >
> > so question, why are you using single ended receiver inputs
> for
> > DPLL lock even though those signal may exhibit a real bad
> jitter?
> >
> > I would think RCV signal (as the only one having correct
> transitions
> > timing in between bits) would be the signal to use for DPLL
> lock?
>
> Yes, that might be a better choice, if your statement
> above is correct. Otherwise it might not, as you loose
> SE0 transitions ...
you dont need to use SE0 to sync bit clock anymore, DPLL
can run few bit times without being resynced so it should
not be a problem.
> > antti
> >
> > PS I have tested the PHY and I know it works OK with real
> world
> > USB applicances, but the question remains :)
>
> If there would be a 40% error I don't think it would be
> able to sync at all. Can you re-verify your claims ?
unfortunatly not so exact I am using fpga on - chip logic analyzer
clocked at 48MHz so I so my view is not very fine grained due do
too low analyzer sampling clock. so logic analyzer sees pretty much
the same data as the PHY sees at same sampling clock.
And yes the signal as seen at 48MHz sampling is as bad that makes
me wonder how does the DPLL still manage it.
> If I remember correctly, USB specifies 0.5% error for the
> clock, so how can the edges of DP and DM be off by 40% ?
see above, I would estimate that edge jitter +/-20% are possible.
and yes it can be - USB spec says clock error, but nothing about
the jitter after single ended receivers. If you look at the internals
of USB11T1A or compatible USB tranceiver then you see 3 different
receivers one each for DP/DM and one for both (The differential one).
the single ended receivers are sometimes also drawn as having
smith trigger funtionality ie built in glitch cancellation, I can easily
believe that the single ended signal and differential receiver signals
differ a lot, what they also do.
this may vary a little depending on the tranceiver chip in use
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