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Message
From: Rudolf Usselmann <rudi@a...>
Date: Sat, 25 Oct 2003 01:14:16 +0700
Subject: Re: [usb] USB 1.1 PHY, DPLL question
On Fri, 2003-10-24 at 19:52, antti@c... wrote:
> Hi Rudolf,
>
> assign change = (rxdp_s0 != rxdp_s1) | (rxdn_s0 != rxdn_s1);
>
> the above is used in DPLL but DP and DM signals are inputs
> from single ended reicevers and have totally different tresholds
> as the differential receiver (e.g. RCV pin on tranceiver chip).
>
> if you look with scope or logic analyzer then the bit widths on
> DP and DM may be wrong as much as 40% percent relative to
> real bit width that under the conditions where RCV signal exposes
> correct bit widths (due to different receiver treshold).
40% error ?! That sounds like a lot.
> the 'change' signal is be '1' during any change on DP or DM,
> but those changes are not always at the same time.
> They should be but with real devices they are not.
> Te signals on DP DM may be actually visually so bad that
> one wonders why is the signal still received ok.
> Well the RCV signal is usually OK
> (if not then of course data transmittion fails already).
>
> so question, why are you using single ended receiver inputs for
> DPLL lock even though those signal may exhibit a real bad jitter?
>
> I would think RCV signal (as the only one having correct transitions
> timing in between bits) would be the signal to use for DPLL lock?
Yes, that might be a better choice, if your statement
above is correct. Otherwise it might not, as you loose
SE0 transitions ...
> antti
>
> PS I have tested the PHY and I know it works OK with real world
> USB applicances, but the question remains :)
If there would be a 40% error I don't think it would be
able to sync at all. Can you re-verify your claims ?
If I remember correctly, USB specifies 0.5% error for the
clock, so how can the edges of DP and DM be off by 40% ?
Regards,
rudi
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