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Message
From: antti@c...
Date: Fri, 24 Oct 2003 14:52:31 +0200
Subject: [usb] USB 1.1 PHY, DPLL question
Hi Rudolf,
assign change = (rxdp_s0 != rxdp_s1) | (rxdn_s0 != rxdn_s1);
the above is used in DPLL but DP and DM signals are inputs
from single ended reicevers and have totally different tresholds
as the differential receiver (e.g. RCV pin on tranceiver chip).
if you look with scope or logic analyzer then the bit widths on
DP and DM may be wrong as much as 40% percent relative to
real bit width that under the conditions where RCV signal exposes
correct bit widths (due to different receiver treshold).
the 'change' signal is be '1' during any change on DP or DM,
but those changes are not always at the same time.
They should be but with real devices they are not.
Te signals on DP DM may be actually visually so bad that
one wonders why is the signal still received ok.
Well the RCV signal is usually OK
(if not then of course data transmittion fails already).
so question, why are you using single ended receiver inputs for
DPLL lock even though those signal may exhibit a real bad jitter?
I would think RCV signal (as the only one having correct transitions
timing in between bits) would be the signal to use for DPLL lock?
antti
PS I have tested the PHY and I know it works OK with real world
USB applicances, but the question remains :)
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