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Message
From: Rudolf Usselmann <rudi@a...>
Date: Wed, 22 Oct 2003 12:07:49 +0700
Subject: Re: [usb] usb1.1 PHY core clock frequency
On Wed, 2003-10-22 at 11:16, tomko@h... wrote:
> I would like to ask some question about FS usb:
>
> 1.why the usb1.1 PHY need to supply with a 48 MHZ(4x data streaming
> rate), can i just input a 12MHZ clock?
>
> 2.what should be the frequency of the clock for the remain usb core
> (UTMI, Protocal Layer.......) , should it be 12MHZ if using full speed
> mode?
>
> 3.Where should the clock of the remain usb core be generate out ? from
> PHY ? or from the external cycstal oscillator?
The USB 1.1 IP has been designed to use a digital PLL to
lock on to the incoming bit stream. In order for the Digital
PLL to work it needs a clock that is 4x the actual bit rate.
Further the core has been designed to use this single clock
(48 Mhz) for all blocks.
You could change it to run on 12 Mhz, but than you would
have to replace the Digital PLLwith an Analog PLL.
> Thank you very much.
Regards,
rudi
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