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From: nalbsr@y...
Date: Thu, 16 Oct 2003 07:31:19 +0200
Subject: [usb] DPLL in usb2.0 / usb1.1 device controller core

Hi ,

I'm working on usb2.0 device controller core.
Can anybody clarify me the requirement of DPLL in the core.

I have 12MHz clock which is the output of a 48MHz crystal as input to 
the SIE. And, PHY_out (30/60MHz ,FS/HS) from the PHY feeding the 
remaning usb core.

Processor interface also runs at 60MHz(ahb).

Now, I'm confused whether I require a DPLL or not.
I'm thinking of one more option - locking the phase of the 12Mhz input 
clock with the phase of phy_out clock(30/60MHz) ,assuming that the 
input data stream is at phy_out clock.

will this idea holds any value?

I have gone through the SIE.pdf at usb.org , confused!

pls. explain me.

Thanks & Regards,
nalbsr