|
Message
From: Rudolf Usselmann <rudi@a...>
Date: Mon, 13 Oct 2003 22:00:50 +0700
Subject: Re: [usb] Size of USB2.0 implementation
On Mon, 2003-10-13 at 21:07, Arius - Rick Collins wrote:
> Thanks for the info. That is a large design. It is over half the
> chip I was looking at using, the XC3S400. Do you think there are any
> features that can be reduced significantly if I work on them? I would
> like to get this down to roughly half the size minus the bus
> interface, about 2000 FF/ 1000 slices. Do you expect this is at all
> feasible?
You really need to do your own trial synthesis. There are
many options that you have to review and decide for yourself
if you need them or not.
>
> BTW, I didn't make the second post because I was getting impatient for
> an answer. I sent the first by email and did not see it in the list.
> I thought that the email did not make it. The second message was
> done directly at the web site.
If you need something really small, look at my usb1_funct.
Thats a USB 1.1 IP core ...
Regards,
rudi
========================================================
ASICS.ws ::: Solutions for your ASIC/FPGA needs :::
..............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools
|
 |
Browse
