|
Message
From: Rudolf Usselmann <rudi@a...>
Date: Mon, 13 Oct 2003 20:16:25 +0700
Subject: Re: [usb] Size of USB2.0 implementation
On Sat, 2003-10-11 at 23:13, Arius - Rick Collins wrote:
> I am looking at the size required for an FPGA I am using in a new
> design. It will have several interchangeable interfaces which will include
> a USB2.0 module. I can't seem to find any info on the implemented size for
> the opencores USB2.0 design. Does anyone have a ball park number I can
> work with? How many FF/LUTs can I expect the USB2.0 design to use?
Sorry, I meant to reply to this earlier, but it slipped my
mind.
For a "xcv400e, package fg676, speed -7":
Number of External GCLKIOBs 2 out of 4 50%
Number of External IOBs 233 out of 404 57%
Number of LOCed External IOBs 0 out of 233 0%
Number of SLICEs 1880 out of 4800 39%
Number of GCLKs 2 out of 4 50%
I believe this was with 4 endpoints.
> How about the UART 16550 core? Anyone have any data on the implemented
> size of that?
>
> I know that the numbers will vary depending on the chip and tools
> used. But I am just looking for a ball park number.
>
> Thanks,
>
>
> Rick Collins
Regards,
rudi
========================================================
ASICS.ws ::: Solutions for your ASIC/FPGA needs :::
..............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools
|
 |
Browse
