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Message
From: amt98007@s...
Date: Fri, 29 Aug 2003 02:53:55 +0200
Subject: [usb] how to correctly operate the usb 1.1 core
Hi!
Me and my colleague are currently developing a USB HID device for a
university project using Rudolfīs nice USB 1.1 core. So far everything
has gone surprisingly well, especially considering us having relatively
limited experience in fpga developing. We have even managed to
implement HID support (at least limited such) into the core without
running into any major troubles. Itīs no doubt that without Rudolfs
great work we would not have come anywere near as far as we have
now! I'll be glad to buy you a beer next time you visit sweden =)
Anyway, back to the subject.. Although everything is currently working
fine, it would be nice to know if we do certain things right when we
operate the core.
For example when reading data from an OUT endpoint: the way we do it
now is that we just look at ep_empty signal. if the fifo is not empty we
read one byte, then we look at the ep_empty signal again, reads one
more byte and so on. This method obviously work, but what happends if
there is a crc error on the payload of the packet? We suspect a better
way to do it would be to wait until the whole packet has arrived in the
fifo, then look at the crc16_err signal before reading the data from the
fifo to be sure it is not corrupted. If so would this be the correct way to
do it?
1. wait until usb_busy = 1 and ep_sel = "our OUT endpoint"
2. wait until usb_busy = 0 or ep_sel != "our OUT endpoint"
3. if crc16_err = 1 clear fifo and return to step 1
4. read fifo contents.
We are also not sure of how to time the fifo:s re and dout signals
correctly (it's a little embarrassing to ask about such a trivial thing.
sorry to bother you with this!). This is how we tried to read two bytes
in a row from the fifo:
@clk: ep_re <= 1
@next_clk: ep_re <= 1, data1 <= ep_dout
@next_clk: ep_re <= 0, data2 <= ep_dout
When we tried this we ended up with the same data in data1 and
data2. What would be the correct way to do this? (We have tried to
simulate the fifo in Modelsim but for some reason the dout signal was
always XX (undefiend) during simulation so it didīnt help us)
Another thing we have been thinking about concerns IN transactions
(bulk & int). It is about how to handle the situations when a packet
sent by the device doesīnt get an ack from the host.
As we can understand it, the function using the endpoint is responsible
to resend the packet when a timeout occure, right? (the core wont
automatically handle this?)
The function can detect when a timeout occured using the int_to_set
and ep_sel signals, right?
This also means that the function must hold a copy of the packet in a
second buffer until it has been ack:ed by the host, right?
If the above is true, how will the function know when an ack has been
received? (so it can proceed with the next packet)
Sorry for the long post, but we would greatly appriciate if someone
could help clear these things out for us. Thanks!
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