Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: mdennis97@h...
Date: Sat, 17 May 2003 18:28:12 -0100
Subject: Re: [usb] Please help with a USB DPLL

hi, Mr. rudi:

I am not so clear about the following code in usb_rx_phy.Maybe there 
are some special functions that I didn't grasp:

// Compensate for sync registers at the input - allign full speed
// clock enable to be in the middle between two bit changes ...
always @(posedge clk)
	fs_ce_r1 <= #1 fs_ce_d;

always @(posedge clk)
	fs_ce_r2 <= #1 fs_ce_r1;

always @(posedge clk)
	fs_ce_r3 <= #1 fs_ce_r2;

always @(posedge clk)
	fs_ce <= #1 fs_ce_r3;

Can I replace them with "assign fs_ce = fs_ce_d;"? If not, why?


Regards

Dennis

Follow up	Author
Re: [usb] Please help with a USB DPLL	Rudolf Usselmann