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Message
From: mdennis97@h...
Date: Sat, 17 May 2003 15:15:50 -0100
Subject: Re: [usb] Please help with a USB DPLL
hi, Mr. rudi:
There is another doubt about the the signal souce of RxEn_i in
usb_rx_phy module. In the phy top module, this signal is connected to
txoe of usb_tx_phy. This txoe, however, if 1, means transmit in process,
if 0, means receiving. At the same time, the clock phase lock control
signal will only function during the receiving period. And this phase lock
need a "1" to drive the DPLL state machine and the Find Sync Pattern
FSM.I am afraid whether this txoe should be negatived before
connected to usb_rx_phy.
Regards
Dennis
----- Original Message -----
From: Rudolf Usselmann <rudi@a... >
To: usb@o...
Date: 17 May 2003 05:43:34 +0700
Subject: Re: [usb] Please help with a USB DPLL
>
>
>
> On Sat, 2003-05-17 at 00:27, mdennis97@h... wrote:
> > > >
> > > > Why not use a static 12Mhz clock for the transmit
> module?For
> > > many
> > > > applications, 12Mhz clock is always available.
> > >
> > > Sure, if all you need is Low Speed, that that would work.
> >
> > One thing should be verified : if only Low Speed is required,
> the fs_ce
> > signal width must be keep 1 clk width(48 Mhz). And in this
> condition,
> > fs_ce works 1.5 Mhz. If the above two requirements are met,
> your
>
> Yes I totally agree with you. That is correct !
>
> > usb_tx_phy module might work except PRE pid which should be
> send in
> > Full Speed.
>
> I believe the PRE PID should be stripped by an separate block.
> This would make the entire design easier. Just watch any traffic
> for PRE PIDs (at the beginning of a new packet), if you see it
> strip it if not, just pass it through.
>
> Good Luck !
>
> --
> rudi
> -------------------------------------------------------
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